There is an increasing demand for miniaturization in the integrated circuits industry. This demand has led to an ever constant reduction in separation between conductive lines (e.g., metal lines) in order to reduce integrated circuit size and/or increase density. The reduced spacing between the conductive lines has the undesirable effect of increasing the capacitance of whatever material lies between the conductive lines. This phenomenon is known as capacitive crosstalk.
In the past, overall integrated circuit (IC) performance depended primarily on device properties, however, this is no longer the case. Parasitic resistance, capacitance and inductance associated with interconnections and contacts of an IC are beginning to become increasingly significant factors in IC performance. In current IC technology, the speed limiting factor is no longer device delay, but the resistive-capacitive (RC) delays associated with the conductive interconnections (e.g., metal lines) of the IC.
Conventional ICs typically employ an interconnect structure wherein a first conductive line is adjacent a second conductive line. If the crosstalk or capacitance between the first conductive line and the second conductive line is high, then the voltage on the first conductive line alters or affects the voltage on the second conductive line. This alteration in voltage may result in the IC being inoperable as a result of misinterpreting logic zeros, logic ones and voltage levels, and consequently incorrectly processing binary and/or analog information.
In order to reduce capacitive coupling and therefore reduce capacitive crosstalk, low dielectric constant (low-K) materials have been developed to lie between conductive lines in order to insulate one conductive line from the other.
FIG. 1 illustrates a portion of a typical integrated circuit. An insulating layer is formed on a semiconductor substrate, both the insulating layer and substrate are generally indicated at 20. A conductive pattern 22 including conductive lines 24 is formed over the insulating/substrate layer 20. The conductive lines 24 are separated by interwiring spaces 26 formed on the insulating/substrate layer 20. A dielectric material 30 (e.g., silicon dioxide, spin on glass) is shown deposited over the conductive lines 24 and the interwiring spaces 26 so as to form an insulative barrier 32 (interlayer dielectric) between the conductive lines 24.
Dielectric materials such as silicon dioxide are susceptible to ion contamination and moisture penetration. Furthermore, current deposition and polishing techniques have not reached a level where contamination of the interlayer dielectric (ILD) is eliminated. Additionally, voids within the ILD may result due to an imperfect fabrication process. Contaminants are undesirable in the ILD because the contaminants may degrade the performance of the ILD and facilitate unwanted capacitive crosstalk (e.g., leakage) between adjacent metal lines. Voids are not desired because the voids weaken the ILD and may lead to the formation of cracks within the ILD which may also give rise to leakage of current between adjacent conductive lines.
Detection of such defects (e.g., lattice defects, dislocations, impurities, contaminants and voids) is typically performed at the end of the process line after the IC is substantially complete. However, the in-line fabrication of the IC represents up to 95% of the cost of the ultimate integrated circuit. Thus, it would be desirable to test the IC during fabrication in order to detect defects in the IC early on before additional monies and man hours are spent down the line for later fabrication steps.
In view of the above, it would be desirable to have a system and method for in-line detection of defects in the interlayer dielectric of an integrated circuit.